Fabrication, Characterization, and Simulation of Highly-Scaled III-V MOS Devices

Abstract

To enable scalable MOSFET technology in III-V semiconductor platforms, high quality semiconductor-oxide interfaces are essential. In this work, the role of surface reactions in the oxide deposition process is examined, with the objective of optimizing the thermodynamics of the semiconductor-oxide interface. A novel low-temperature plasma-enhanced atomic layer deposition (PEALD) technique was applied to deposit nanoscale high-k dielectrics on several III-V substrates, including InP, GaAs, InAs, and GaN. Approximately 7 nm of ZrO2 was grown and patterned to form MOSCAP structures, which were subsequently analyzed through electrical characterization to evaluate dielectric and interface quality. The oxide films fabricated were found to have interface trap densities ranging from 1010-1013 eV-1cm-2, and showed high capacitance densities (~2.5 μF/cm2). GaN and InP MOSCAPs with ZrO2 dielectric layers were found to have gate currents in line with direct tunneling phenomena and MOS mobilities approaching that of doped bulk semiconductors. Scaled InP MOSFET devices using these experimental oxide results were also simulated using improved device structures, with the aim of demonstrating optimal parameters for effective reduction of short-channel effects. These devices demonstrated high performance for various scaled gate lengths, with FinFET structures showing excellent frequency response at the 7 nm process node.