Real-Time Hardware-in-the-Loop Emulation of Electric Machines for Electrified Transportation Systems
Date
Author
Institution
Degree Level
Degree
Department
Specialization
Supervisor / Co-Supervisor and Their Department(s)
Citation for Previous Publication
Link to Related Item
Abstract
Design and prototyping of electric power components and systems employing off-line transient simulation tools are inefficient due to, first, time consumption of sequential processors for several cycles of testing, and second, inaccuracy arising from simplifications in the modeling of the entire system. Hardware-in-the-loop (HIL) emulation can massively accelerate the design procedure and provide a highly accurate testing platform for the manufactured prototype devices to interact with the rest of the system model on a simulator in a nondestructive environment before commissioning. The scenario is efficient when the emulated system computations can be executed in real-time with a specified time-step which is small enough to model all the transients of the system. Field programmable gate array (FPGA) proposes an attractive platform for real-time simulation due to reconfigurability, widely paralleled, deeply pipelined architecture and low input/output latencies. As a key component of the power systems with a wide variety of applications, testing of electric machines in the design and control procedure for the purposes of energy efficiency and performance improvement is becoming increasingly demanding. The complex structure of electric machines makes real-time simulation challenging mainly due to mechanical movement and magnetic nonlinearity. This thesis addresses challenges and solutions for real-time HIL emulation of electric machines. Comprehensively, all three widely used electric machine models including q-d vector model, magnetic equivalent circuit, and finite element method models are investigated for real-time simulation of low power rotary induction motor and high power linear induction motor for magnetic levitation application. An evaluation in terms of real-time step-size and accuracy as well as FPGA hardware resource utilization corresponding to each model is provided. The validation of results with off-line transient simulation and finite element tools and experimental measurements demonstrates the accuracy and efficiency of the proposed approaches.
