High-speed alias-locked loop frequency synthesis

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dc.contributor.authorVan Den Berg, Leendert Jan
dc.date.accessioned2025-05-29T15:01:29Z
dc.date.available2025-05-29T15:01:29Z
dc.date.issued2008
dc.identifier.doihttps://doi.org/10.7939/r3-jbgw-rv62
dc.language.isoen
dc.rightsThis thesis is made available by the University of Alberta Libraries with permission of the copyright owner solely for the purpose of private, scholarly or scientific research. This thesis, or any portion thereof, may not otherwise be copied or reproduced without the written consent of the copyright owner, except to the extent permitted by Canadian copyright law.
dc.subjectFrequency synthesizers.
dc.subjectPhase-locked loops.
dc.subjectFeedback control systems.
dc.titleHigh-speed alias-locked loop frequency synthesis
dc.title.alternativeAlias-locked loop frequency synthesis
dc.typehttp://purl.org/coar/resource_type/c_46ec
thesis.degree.grantorUniversity of Alberta
thesis.degree.levelMaster's
thesis.degree.nameMaster of Science in Computer
ual.date.graduation2008
ual.departmentDepartment of Electrical and Computer Engineering
ual.jupiterAccesshttp://terms.library.ualberta.ca/public

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