Digitally Enhanced SNR Optimized CMOS Optical Receiver

Abstract

The continuing exponential increase in functionalities of integrated circuits demands high data rate intra-chip and inter-chip communication. However, high speed communications inside silicon chips are often bottlenecked by capacitive drain of the channels. Therefore, as the functionalities of integrated circuits get increasingly sophisticated, achieving the required high bandwidth operations becomes increasingly challenging. Photonic integrated circuits (PIC) are considered as a potential solution, where electronic signals are converted into optical signals and transmitted through waveguide structures. The optical signals are converted back to the electronic domain by photodiodes at the receiving end and then processed by optical receivers. In order to maintain the high data rate operation of the system, the optical receivers must be optimized to perform at high bandwidth. This thesis focuses on enhancing the SNR performance of optical receivers.

The first work of the thesis describes a high gain-bandwidth transimpedance amplifier (TIA) with optimized SNR. The design uses a common gate TIA as the first stage and then the gain and bandwidth is enhanced in the subsequent stages using various techniques. The design is implemented in ST 28-nm FDSOI CMOS technology; it achieves a transimpedance gain of 55 dBΩ and 3dB bandwidth of 32 GHz. The second work of the thesis focuses on designing an energy efficient inter symbol interference (ISI) equalizer. It proposes an Analog to Sequence Converter (ASC) based Maximum A Posteriori (MAP) decoding equalizer. The concept was implemented in 0.13 μm CMOS technology. The implemented prototype is capable of compensating 35+ dB loss at 10 Gb/s data rate with better than 10 pJ/bit energy efficiency.