Accelerating FPGA Design Space Exploration Using Circuit Similarity-Based Placement
| dc.contributor.author | Lin, Guohui | |
| dc.contributor.author | Shi, Xiaoyu | |
| dc.contributor.author | Hu, Yu | |
| dc.contributor.author | Zeng, Dahua | |
| dc.contributor.author | Zaiane, Osmar | |
| dc.date.accessioned | 2025-05-01T21:12:49Z | |
| dc.date.available | 2025-05-01T21:12:49Z | |
| dc.date.issued | 2010 | |
| dc.description | Technical report TR10-04. This paper describes a novel and fast placement algorithm for field programmable gate array (FPGA) design space exploration. The proposed algorithm generates the placement based on the topological similarity between two configurations (netlists) in the design space. Thus, it utilizes the sharing of reusable information during the design space exploration and avoids the time-consuming placement computation like versatile place and route (VPR). Tested on logic-level and algorithm-level design space exploration cases, our similarity-based placement accurately depicts the \"shape\" of a design space and pinpoints the designs which are of most interest to IC designers. Moreover, a turbo version of circuit similarity-based placement performs an average of 30x (up to 100x) faster than VPR's while still achieving comparable placement results. | TRID-ID TR10-04 | |
| dc.identifier.doi | https://doi.org/10.7939/R38Q8M | |
| dc.language.iso | en | |
| dc.rights.uri | http://creativecommons.org/licenses/by/3.0/ | |
| dc.subject | FPGA | |
| dc.subject | Placement | |
| dc.subject | Graph similarity | |
| dc.subject | Artificial Intelligence | |
| dc.subject | Algorithmics | |
| dc.title | Accelerating FPGA Design Space Exploration Using Circuit Similarity-Based Placement | |
| dc.type | http://purl.org/coar/resource_type/c_93fc | |
| ual.jupiterAccess | http://terms.library.ualberta.ca/public |
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