Device-Level Power Electronic System Emulation for Hardware-in-the-Loop Applications

Abstract

Hardware-in-the-loop (HIL) simulators are prevalent in many industries and are playing a significant role in the design and testing of new equipment. While detailed models of power system components are available for HIL simulators, there is limited knowledge in the area of power electronic converter modeling. Currently available HIL simulators employ simpler models for power electronic converters, based on ideal or averaged switch models. While such models are adequate for system-level performance evaluation and analysis, there are seldom sufficient for the analysis of device-level stresses, electromagnetic interference (EMI), and parasitics, which are especially important at high switching frequencies. This thesis develops device-level models for power electronic converters for HIL simulation. Detailed device-level hardware models are developed for the insulated-gate bipolar transistor (IGBT) and the power diode on the field-programmable gate array (FPGA). The hardware design are fully paralleled using an IEEE 32-bit floating-point precision to achieve the lowest latencies and resource consumption. An efficient variable time-stepping algorithm is proposed for the solution of the nonlinear device equations. Case studies for DC-DC and DC-AC converters are emulated and validated, showing good agreement.